资源列表
dds
- FPGA所需要的DDS源码，可实现波形输出，采用VHDL语言，简单易懂。-FPGA need DDS source waveform output can be achieved using VHDL language, easy to understand.
VHDL
- VHDL下的自动售货机的源码和设计思路，希望给大家有一定的启发-VHDL source code under the vending machines and design ideas, want to give you a certain degree of inspiration
UART(FPGA)
- 基于现场可编程逻辑器件（FPGA）使用VHDL语言QuartusII实现UART通讯-Based on field programmable logic device (FPGA) using VHDL language QuartusII achieve UART communications
shizhong
- VHDL设计带报警的59分钟定时器，系统以秒速度递增至59分钟后,启动报警1秒钟,置位后又以秒速度递减至零并报警1秒钟。-VHDL design with alarm 59 minutes timer
MIPS
- 5个stage的pipeline MIPS，支持着JUMP，BRANCH等跳转命令。-simple 5-stages MIPS structure which supports forwarding commands.
Electronic-Design-Automation-Vhdl
- 各种计数器，编码器，全加器等元件的VHDL语言描述-A variety of counters, encoders, such as full-adder components described in VHDL language
Power_Supply_Integrity
- altera的FPGA电源完整性白皮书，提供了旁路、去耦电容大小的计算-altera s FPGA power supply intergity
SDRAM_HY57V6416ET
- 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M * * 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
hyalite3
- 数字钟1、具有时、分、秒计数显示功能，以二十四小时循环计时。 2、具有清零，调节小时，分钟的功能。 3、具有整点报时同时LED灯花样显示的功能。 -Digital clock 1, with hours, minutes, seconds count display features cyclic timing twenty-four hours. 2, has cleared, adjust the hours, minutes function. 3, with the patt
CPU_Project_board
- CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）-5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce)
FPGA
- 很好的VHDL程序段，可以帮助迅速了解和提高编程水平-Good VHDL program segment can help to quickly understand and improve the level of programming
UART
- 在过程控制板上实现8051F340的串口通信功能-Control board in the process of serial communications to achieve 8051F340