资源列表
fpga_chkdiv
- 本文档为fpga的时钟分频实验代码，初学者可以参考使用。-fpga clock divider source code。
8051core-Verilog
- 用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！-Verilog FPGA internal 8051 core, super, super hard to find! Shared out!
Verilog-classic-tutorial
- Verilog经典教程，非常好的资料！值得一看！-Classic Verilog tutorials, very good information! Worth a visit!
ethernet
- 一个典型的以太网的VHDL程序，非常有参考价值！！ -A typical Ethernet VHDL program, a very valuable reference! !
can
- 一个典型的CAN总线的VHDL程序，非常有参考价值-A typical CAN bus VHDL program, a very valuable reference! !
NiosII-example
- NIOSII电路设计 ，经典的实例祝你在学习中更准确的掌握工作中实用的技术！-NIOSII circuit design, classic examples I wish you a more accurate grasp of the practical technical work in learning!
UART-VHDL-design-
- 设计的VHDL串口实例，感觉还不错，可以拿来借鉴和修改啊！-Design VHDL serial instance, I feel pretty good, can be used to draw and modify ah!
VHDL-design-example
- VHDL综合设计实例，很好的参考资源，让你快速进入VHDL学习的殿堂！-VHDL design examples, a good reference resources, lets you quickly enter VHDL learning the hall!
sipo
- shifter unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
register
- register designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
multiplexer
- multiplexer unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
andgate
- and gate unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.