资源列表
cic
- 抽取滤波的Verilog实现，经测试可用-Decimation filter
lcdDriver
- LCD Vhdl module controller for HD47780 driver. The program writes some data to the LCD.
div
- 自己编写的一个计数器分频，通过调整计数周期和计数值，可以获得不同频率，不同占空比的分频时钟-I have written a counter divider by adjusting the count period and the count value can be obtained at different frequencies, different duty cycles of the divided clock
reg
- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out
pcirw
- quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序，可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,bla
smart
- 周立功的SmartEDA中的串口源码，照着书本敲入电脑的-ZLG' s SmartEDA the serial source code, according typing computer books
tb_gen_mag_comp
- magnitude compararot which is used to comapre the bits
lab2_2
- multiplier using basic gates and full adders-4 bit array multiplier
GPIF
- 实现USB高速传输,使用了GPIF模式，用的是CY7C68013-USB transmit in high speed
PULSE_CDC
- Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock -Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock
PS2_verilog_source
- 在vhdl开发环境下，关于协议PS2 verilog 源码
TOP_DATE
- Code to have an incremante date