资源列表
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- 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
div_res
- 这是一个用VERILOG实现的除法的指令，用状态机实现的，希望对大家有用-THIS IS A CODE FOR DIV OF VERILOG。ITS USEFUL...
F5D
- 这是用verilog硬件描述语言编的5分频代码-This is verilog hardware descr iption language code is compiled by five divider
uart_tx
- this code is in VERILOG HDL .. its for serial communication ..it allows serial data transmission from FPGA to computer
multiplier__tb
- paralel multiplier with booth coding in verilog
time12
- Program demonstrate time24 to time12 object conversion.
fir4
- 基于vhdl的长度为4的fir滤波器，经过官方软件认证-Based on the length of 4 vhdl fir filter, after the official software certification
traffic-lightr
- 课堂实验交通灯源码，交叉路口上状态切换次序为（复位）红红－红绿－红黄－绿红－黄红－红绿。南北和东西分别对称。-Classroom experiment traffic light source, crossing state switch on the order (restoration) red red red, green, yellow and red--green red-yellow, red and green- North and south and things were sy
VHDL-DDS
- 基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率-FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency
lab_6_1
- 用VHDL描述的74ls163,模拟实现其时序逻辑功能-Using VHDL described 74ls163, simulation to achieve its sequential logic functions
SevenSegmentDisplay
- VHDL预压7端数码管 利用不同的两种方法实现-7-end digital works two ways to achieve
51_cpld_bus
- 实现51单片机与cpld的总线连接,经过调试，希望对大家由用-MCS51 and cpld interface using bus method