资源列表
sim_nandflash
- 完成FPGA对NAND FLASH的读写操作，整个控制构架搭设完毕，可以添加新的功能。板级验证正确，有仿真波形和三星NAND FLASH 手册。-FLASH read and write operation to complete, board-level verification is correct for the new to FLASH friend, a simulation waveform and Samsung FLASH Manual
PWM
- pic单片机的脉冲宽度设置程序，虽然程序非常的简单，但是能够自由的调整脉冲宽度-pic microcontroller pulse width of the setup program, although the program is extremely simple, but the freedom to adjust the pulse width
FPGA--VerilogFIFO
- FPGA串口通信程序 基于fifo读写的串口通信程序-FPGA serial communication program is based on the serial communication program to read and write fifo
cd_player_vhdl
- 全套日本CD Player的FPGA设计制作源码(用VHDL编写)。在ise上运行。-Japanese CD Player complete set of FPGA design source (using VHDL). Ise on the run.
my
- 64位数据的CRC-32校验的，Verilog实现，算法并行优化-64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm
xc2v_verilog
- MIMO Simulation VHDL code
xc2v_vhdl
- Verilog Code for MIMO system
Xilinx_PCI_Express_IP_project
- Xilinx公司PCI Express IP核应用参考设计
canopen-spec
- CANopen协议的详细说明，清楚的解释了什么是对象字典，以及SDO，PDO的通信规范，对CANOPEN通信状态机也作了说明。-CANopen protocol details, a clear explanation of what is an object dictionary, and SDO, PDO' s communications standards, for CANOPEN communication state machine are also described.
__DVI.ZIP
- Obsł uga wejś cia/wyjś cia DVI (C) Xilinx
EDA_FPGA_240i2c-master-slave
- 用硬件语言实现的I2C程序，主从都包括，从而实现主从之间的通信-Using the I2C hardware language program, including master and slave are, in order to achieve the communication between master and slave
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language