资源列表
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
FPGA-Prototyping-By-Verilog-Examples
- 通过Verilog例子了解FPGA原型设计（书和源码）-FPGA Prototyping By Verilog Examples
LCD1601
- ＬＣＤ１６０１在８０５１上的驱动，可在屏幕上显示任意字符-LCD1601 driver in 8051 can be any character on the screen
UART_Quartus_verilog
- 用Verilog编写的异步串口通信程序，开发环境为Quartus II，具有一定的参考价值。-Written in Verilog asynchronous serial communication program development environment for the Quartus II, with some reference value.
mcp23s17
- c for microchip spi io expander mcp23s17
hydrophone-and-vector-hydrophon
- 介绍光纤水听器和矢量水听器的原理、性能等，并给出各自的优缺点-Introduce fiber-optic hydrophone and vector hydrophone principle, performance, etc., and give their advantages and disadvantages
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
VHDL-FPGA
- FPGA使用经过优化的x264编码器速度大概是网上公布的x264版本的三倍，质量下降约0.2db，码流增大约5％。已成功应用于多家公司的视频会议。 一共有三个文件夹： 1，x264编码可执行程序-this is tool for FPGA with VHDL!
chip-SRAM-communication
- Verilog编写FPGA与片外SRAM通信模块，内含源代码，希望对大家有所帮助。-FPGA in Verilog-chip SRAM with communication modules, including source code, we want to help.
VHDL-digital-clock-
- VHDL编写的数字钟，采用元件例化的方法，可实现调秒 调分 调时 报时 闹铃的功能 开发板使用的是EP3C16Q240C8-Digital clock written in VHDL, using the example of the way components can be adjusted to achieve sub-second tone when the alarm tone Times feature development board using EP3C16Q240C8
RC6-block-cipher-using-VHDL
- VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped
Verilog
- 针对Verilog语言，提供了135个经典的示例程序代码，从简单到复杂，一步步的深入。-For the Verilog language, providing 135 classic example code, from simple to complex, step by step in depth.