资源列表
uart_TEST
- verilog实现串口通信实例程序源代码，以在自己开发板上实现-Serial communication example verilog source code to implement in their own development board
dma_0
- SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
gaosizaosheng
- 高斯白噪声的FPGA实现文档，讲解的比较全面。-FPGA Implementation of Gaussian white noise documents, a more comprehensive explanation.
adpeizhi
- ad9716，ad9235的FPGA配置，可以对ad9716，ad9235完成完整的FPGA配置，很好-ad9716, ad9235 FPGA configuration, you can ad9716, ad9235 complete a full FPGA configuration, good
AHB-BUS-AND-SLAVE-CODE-USING-VERILOG
- AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
Program3
- 用 vhdl 语言设计 8 位数码扫描显示电路，显示输出数据直接在程序中给出。增加 8 个 4 位锁存器作为输出显示数据缓冲器，由外部输入8个待显示的十六进制数。-Design with vhdl language display 8-bit digital scanning circuit, display output data are given directly in the program. Increased eight 4-bit latch display data buffer
EP3C16_Nios_LCD12864
- 基于ep3c16-nios的12864液晶的驱动程序，简单明了，适合新手学习。-Based on ep3c16-nios 12864 LCD driver, simple and clear, suitable for novice to learn.
rx_fifo
- verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
awg
- 基于FPGA的任意波形发生器源代码，并且添加了上位机发送指令和数据（低八位用来发频率控制字，高八位用来发指令）。-FPGA-based arbitrary waveform generator source code, and add the host computer to send commands and data (low eight frequency control word is used to send high eight used to send commands).
unsig_altmult_accum
- 无符号型的基于累加器的乘法器，代码比较简单-unsigned altmultiplex accumultor
CCD_CPLD
- 内部资料，CCD探头采集时序发生器，基于CPLD用VHDL编写，是学习CPLD和VHDL在实际工业应用中的实际案例。-Internal information, medical collection probe CCD Timing Generator, based on the CPLD using VHDL, CPLD and VHDL to learn practical industrial applications in the real case.
FPGA_DDS
- FPGA中实现信号发生器,即DDS,代码简洁,精练,非常适合学习,已经经过验证.-The FPGA signal generator, or DDS, the code simple, concise, very suitable for learning, has been verified.