资源列表
tb_counter
- vhdl code for counterand detemines how counter works
cont10_v.sym
- 十进制计数器既可采用QuartusII的宏元件74160，也可用VHDL语言设计。在项目编译仿真成功后，将设计的十进制计数器电路设置成可调用的元件cont10_v.sym，用于4位十进制计数器的顶层设计。-Decimal counter can use QuartusII macro components 74160, also available VHDL language design. After the success of the project compiled simulation
hdb3enc_rtl
- hdb3编码，实现很简单，实际验证过，可以用。-hdb3 coding to achieve is very simple, actually verified, you can use.
seven-segment-display
- seven segment diaplay
rom
- ROM模式的实现机制，基于verilog语言。-Implementation mechanism of ROM model, based on Verilog language.
mode_det
- 用于检测时钟的有无，通过输出的信号电平进行指示-For detecting the presence or absence of the clock, by the output signal level is indicated
binarytree
- Binary tree in system verilog using classes, and automatic function
SYNC_FIFO
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
hello_world_small
- 采用altera mac核加88e111物理层芯片的千兆网方案，该文件是配置mac层和物理层的nios文件，基于hello world small工程。-88e111 by altera mac core and Gigabit Ethernet physical layer chip of the program, the file is configured mac layer and physical layer nios file, based on hello world small
demux81
- VHDL Code for DEMUX using when
netAD0809
- verilog描述的AD转换，简要的描述的AD转换的过程-verilog descr iption of AD
SignedMul18x18
- This my version of the scale, and the multiplier block, which can be used in digital devices-This is my version of the scale, and the multiplier block, which can be used in digital devices