资源列表
ANSWER
- 采用VHDL设计的抢答器，抢答时间10秒钟，10秒内无人抢答，则抢答按键失效。显示抢答的队伍号。适合做课程设计。-Design using VHDL Responder, Responder for 10 seconds, no answer in 10 seconds, then the answer in key failure. Display answer in team numbers. Suitable curriculum design.
Digital-tube-display-module
- 通过控制模块送来的数据对数码管进行动态扫描显示-Through the control module of the data sent to digital tube dynamic scanning display
jiaotong
- 用xilinx的spartan3做的红绿交通灯，带有夜间模式-With of xilinx spartan3 do red and green traffic lights with night mode
CMI-code
- cmi docer,verilog语言，已验证。-cmi docer, verilog language, has been verified.
LFSR
- lfsr implement in fpga
AUTO_SELL_DRINK
- 这是用verilogHDL语言编写的自动出售饮料的电路。会根据顾客投入硬币的多少来送出饮料，并且找回零钱。-This is language used verilogHDL automatic circuit the sale of beverages. Customer input will be based on the number of coins out drinks, and get back change.
memory
- the memory program are used to design the fpga application for in very log module
Muliply
- 16-bit multiplier in VHDL
slave_tb
- 实现对slave模块仿真的tb，利用三态始能实现。-verilog slave tb is useful
counter4
- 四位数码管计数，可以从0000一直计数到9999，用七段数码管显示。- 4 data counter，you can use it to count from 0 to 9999.
Part3
- Quartus for 8x8 multiplier using lpm mult module from the library of parameterized modules in the Quartus II system.
true_dual_port_ram_single_clock
- Quartus II VHDL Template. True Dual-Port RAM with dual clock.