资源列表
ps2
- fpga ps2接口控制 能够实现ps2键盘扫描 在数码管上显示出相应编码-fpga ps2 interface
ClockOut
- 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
keyscan_test
- 针对机械式按键存在的抖动问题，用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块，已经在ISE综合通过！-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
sipo
- Serial In Parallel Out Shift Register in VHDL in Modelsim
LTC1407A
- LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
decode
- 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
FIR_1
- FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
FIR_filter_DA_machine
- 用verilog 代码编写的179阶FIR数字滤波器，采用分布式算法实现-verilog code used to prepare the 179 band FIR digital filters, using Distributed Algorithms
bujindianji
- 这是汇编语言，用VHDL语言编的步进电机程序
2-4
- 2-4译码器 -2-4 decoder
time_stamp
- 基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines