资源列表
eda-Lab-report
- 三线八线译码器、数据选择器、数据比较器、二进制编码器、译码器的verilog语言输入方法-Three line eight line decoder, data selector, comparator, the binary encoder and decoder of verilog language input method
digital_clock
- 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习
sopcniosexample
- 通过quartusII的sopc构建一个简单的nios系统，里面还有简单nios实例，操作步骤很详细-Sopc through the quartusII to build a simple system nios, nios there is also a simple example of the steps in detail
ADCGraph2
- VHDL PROGRAM & LAB SOLUTIONS
SEED-XDS560PLUS
- SEED-XDS560PLUS仿真器安装、使用指南-SEED-XDS560PLUS simulators installation, use guide
RelojAlarma
- This the code done to execute a alarm clock digital-This is the code done to execute a alarm clock digital
VGA
- 用FPGA驱动VGA显示器并控制VGA显示部分俄罗斯方块以及横条、竖条、棋盘格等-Driving with FPGA VGA VGA display and control the display part of the Russian box and bar, vertical bar, checkerboard, etc.
123
- 系统介绍了数字开发系统平台FPGA设计中的部分技巧 对于FPGA开发研究人员具有一定的指导和帮助意义-Systematic introduction of digital development platform FPGA design techniques for FPGA development of some of the researchers have some sense of guidance and help
LIU
- dda 插补法中 由vhdl 语言来实现-dda interpolation achieved by the vhdl language
Verilogstudy
- 该资料介绍了Verilog编程的入门和应用，对初学者帮助很大，希望能帮助到大家！-Verilog study
multiplex
- 四路信息时分复用和解复用，包含串并转换，并串转换，提取帧同步，分频，移位寄存器。-Quad information time-division multiplexing and demultiplexing, contains the string conversion, parallel-serial conversion, extracting the frame synchronization, frequency division, the shift register.
qep_data_bus
- 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的-address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL