资源列表
gtx_interface_ip
- 高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
pwm
- 通过分频产生信号，与三角波比较产生pwm-By dividing the clock signal is generated, compared with the triangular wave generated pwm
testfreq
- 利用示波器的X和Y通道输出采样波形图形 注：显示两个周期。扫频频率100Hz
uart_tx1
- UART TX spartan 3e starter kit
EP1C3_12_1_2_MOTO
- 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
f_changed_sin_wave
- 用RAM实现频率可调正弦波发生器，开发环境：Quartus8.0-To frequency tunable sine wave generator development environment: Quartus8.0 using RAM
VGA
- Make adjustments in VGA by FPGA
DE2_synthesizer
- build synthesizer on a de2 dev fpga board
E4_6_FirIpCore
- 对软件自带的fir 核进行相关配置，仿真测试其功能，同时完成相关滤波作用，观察其输出波形(The configuration of the fir kernel is simulated, the function is tested, the function of correlation filtering is observed, and the output waveform is observed.)
DDSIP
- 该程序实现了正弦函数与余弦函数数据的产生，可作为其他模块的输入信号（可以直接调用）-The program implements a sinusoidal function and cosine function data can be used as an input signal to other modules (direct call)
UART
- 利用Verilog实现UART收发数据功能-Verilog UART send and receive data functions to achieve
EDA
- 毕业设计时设计的一个基于FIFO的乒乓机制，作用是不用等待当前数据接收完后再处理，提高数据吞吐量。-A graduate of the design in the design of a FIFO based on the ping pong mechanism, effect is not waiting for the current data received after processing, improve the data throughput