资源列表
shuzitongxinxitongjianmo02
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第一部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the first part of the digital communication syste
Ripple_Carry_counter
- Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.
Ripple_Counter
- Ripple carry counter with 4 bit resolution implemented in behavioral VHDL. attaches as well is a jpg with the logic gates bock diagram. this is an asinchronous design.
4bitMultiplier
- 4 bit multiplier implemented with behavioral VHDL code. in addition a visio shceme is attached along with a jpg copy for thoese fho dont have visio.
mux4x1
- mux 4x1 with 2 control inputs, written in VHDL using 3 mathods: Logic gates, if, case. the fastest model is the one implemented with the case code.
CoreI2C
- CoreI2C实验的源代码-Experimental CoreI2C source code. . . . . . . . . . .
Multiplier
- 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
exemple_fifo_GradHori
- example filtre, framer-example filtre, framer..
Xilinx_XUP_V2P
- Please read your package and describe it at least 40 bytes in English.
DE2_70_TV
- --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor shoul
Sn_Quartus
- Frequency synthesizer VHDL
DigitalDesignwithCPLDandVHDL
- Digital Design with CPLD and VHLD ebook worht downloading-Digital Design with CPLD and VHLD ebook worht downloading