资源列表
3-to-8Decoder
- 3 to 8 Decoder in vhdl
16-1MUX
- 16 down to 1 Multiplexer in Vhdl
IIR
- VHDL语言编写的IIR滤波器，实现IIR功能-VHDL language of the IIR filter, the realization of IIR function
UART_Rcvr
- uart 的源程序，用verilog编写-uart
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
counter
- this is a code for sequenc detector
HDB3_decoder
- 用VerilogHDL实现了HDB3码到NRZ码的解码过程-decode HDB3 code to NRZ code using VerilogHDL
HDB3
- 用VerilogHDL实现了从NRZ码到HDB3码的编码过程-NRZ code to HDB3 code using VerilogHDL
clock_divider
- This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
P2S_SM
- This file contains the state machine which has the control signals required for the parallel to serial conversion-This file contains the state machine which has the control signals required for the parallel to serial conversion....
P2S_TOP
- This file contains the Parallel to Serial conversion. This is the top module where we can change the code. The other part of this file is Parallel to Serial controller i,e P2S_SM
S2P_TOP
- This file contains the top module which uses the S2P_SM module which is actually a controller. SO by changing in the top module we can use the S2P module completely-This file contains the top module which uses the S2P_SM module which is actually