资源列表
SDRAMcontrollor
- SDRAM控制器，以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz，我在实际工程中用到了120MHz，但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the
verilogHDL
- <精通Verilog HDL语言编程>随书光盘源码-Verilog HDL
vhdl-JPEG-enc
- JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
gray_cnt
- 一个格雷码计数器，利用Verilog语言实现，一个初学者的好例子。-A Gray-code counters, the use of Verilog language, a good example for beginners.
intro_to_quartus2_chinese
- 详尽的quartus中文版介绍，使用方法，技巧等-failed to translate
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
m_decode
- 关于ISO18000-6c协议中反向链路的编码实现没有最终调通-failed to translate
usb-blaster
- quartus多种USB-bletera 自制下载线！
wave_generator
- 基于cycloneII的信号发生器，产生正弦波、方波、三角波，人机界面十分友好，可方便地进行波形切换-CycloneII based on the signal generator to produce sine wave, square wave, triangle wave, a very friendly man-machine interface can be easily switched waveform
iclock
- 基于cycloneII的电子时钟，可实现手动调整时间，良好的人机界面，简单易用，编程结构清晰-CycloneII-based electronic clock, can be manually adjust the time, a good man-machine interface, easy-to-use, structured programming
fre_pha_measure
- 实现了基于cycloneII的信号相位、频率测量，经测试可用-CycloneII based on the realization of the signal phase, frequency measurement, the test can be used
VHDlclock
- 数字秒表的VHDL课程设计 通过硬件测试 精确到ms 最大可计时为24小时 -Digital stopwatch curriculum design through the VHDL hardware testing is accurate to ms maximum time of 24 hours