资源列表
interleaver
- 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
SRAM_with_con
- 带有控制器的SRAM，提供一个地址选通脉冲ADS，一个读/写信号R_W,一个时钟信号和复位信号，包含了测试文件。-Controller with the SRAM, providing a strobe pulse Address ADS, a read/write signal R_W, a clock signal and reset signal, including the test documents.
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
cordicCOS
- 用CORDIC算法来实现y余弦运算，并在QUARTUS2中仿真通过，误差较小。-CORDIC algorithms used for cos .
QuartusMaxplus
- VHDL语言工具的学习，是硬件描述语言开发环境的学习。-VHDL language learning tools, hardware descr iption language development environment for learning.
frequency_divide
- 本程序用verilog编写，实现了任意整数分频-Arbitrary integer frequency_divider
11
- VHDL针对FPGA的代码风格 FPGA内部结构 如何运用原语.-VHDL code for FPGA style FPGA internal structure how to use the original language.
ps2_verilog
- 用Quartus II 7.2 开发的ps2键盘与计算机串口通讯的程序-Quartus II 7.2 with the development of the ps2 keyboard and the computer serial port communication program
undistort
- floating point arthematic function with verilog code
gh_timer_8254_1_1
- opencores的8254vhdl源代码，只需修改总线接口即可使用-8254vhdl the opencores source code, just modified to use bus interface
traffic
- 交通灯 vhdl 进程
gh_vhdl_lib_3_47
- Opencores的VHDL元件库3.47版-The VHDL component library Opencores version 3.47