资源列表
uart
- 使用VERILOG实现自己定以的UART算法，只要自己看懂了，再修给下下就可以使用了-VERILOG use to achieve their own set of UART algorithm, as long as my understood, and then repair to the next can be used under
MulAddAbs
- 9 bit multiplier in VHDL
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
uart
- 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and ove
Altera_timing
- 本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle
FIR_Filter_Base_on_FPGA
- 详尽的讲述了FIR滤波器在FPGA上的实现思路-Detailed story of the FIR filter in FPGA realization of ideas
cpu(FinalWithYS)
- verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
vhdl
- VHDL的论文，有关出租车计费器的设计，很好。-VHDL
vhdl1
- VHDL的几种状态机，双进程单进程以及其它类型。-Several VHDL state machine, dual-process single process, as well as other types.
vhdl
- 通用寄存器，移位寄存器，简单状态机，直流电机控制器，-General registers, shift register, a simple state machine, DC motor controllers, etc.
a
- EDA技术正在成为主流的电子系统设计。可编程逻辑器件基于FPGA -EDA technology is becoming the mainstream of electronic system design. Programmable Logic Device Based on FPGA,
chengfa
- 我做的组成原理课程设计！用VHDL实现加法树的乘法。-I do the composition of the principle of curriculum design! VHDL adder tree used to achieve multiplication.