资源列表
cymometer
- 数字频率计的源码 最大测量频率达到30MHz-Digital frequency meter measuring frequency of the source code to achieve the maximum 30MHz
asynchronoussignal
- 描述跨时钟域分析,分析和解决异步时钟同步设计问题.-Descr iption of cross-clock domain analysis, analyze and solve design problems in asynchronous clock synchronization.
I2C_receiver
- 自己写的一个i2c slave的模块，verilog，已经通过验证，可以写可以读，希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
divide_by_3
- This module divides the input clock frequency by 3.
aFifo
- This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001.
syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit
cam
- This Verilog desription shows an example for a Content Adressable Memory (CAM)
uart
- This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
filtru_fi
- This is a filter fir implemeted in vhdl, i hope it will work :)
cronometro
- This the program of a timer with a accuracy of ms-This is the program of a timer with a accuracy of ms
EDA_tel_counter
- 在EDA教学试验箱上（忘了学校的试验箱型号了）实现电话计费器功能-EDA teaching in the chamber to achieve telephone billing function
PS2_IP_CORE
- 该IP核是一个ps2键盘的源代码（vhdl语言）-The IP core is a ps2 keyboard source code (vhdl language)