资源列表
auto-sale-machine
- 自动售货机程序，适合FPGA初学者，作为参考吧。-Vending program for FPGA beginners, as reference to it.
calling-cost-program
- 电话计费FPGA程序，作为一个简单开发FPGA不错的程序，希望对大家有用。-Telephone billing FPGA program developed as a simple FPGA good program, we hope to be useful.
Dual-port-RAM-data-acquisition
- 利用传统方法设计的高速数据采集系统由于集成度低、电路复杂，高速运行电路干扰大，电路可靠性低，难以满足高速数据采集工作的要求。应用FPGA可以把数据采集电路中的数据缓存、控制时序逻辑、地址译码、总线接口等电路全部集成进一片芯片中，高集成性增强了系统的稳定性，为高速数据采集提供了理想的解决方案。-Using traditional methods of high-speed data acquisition system design due to low integration, circuit
Posedge-Detection-Circuit
- Verilog脉冲边沿检查，此代码包含完整的工程，利用quartus软件可以直接运行仿真。-Verilog edge of pulse examination, this code contains the complete engineering, quartus software can be used to directly run the simulation.
div_3
- 用Verilog实现时钟三分频，该代码包含完整的工程文件，可直接运行。-The realization of clock frequency of three Verilog, the code contains the complete engineering documents, can be directly run.
FIR
- 基于Verilog的FIR滤波器的设计，该代码包含完整的工程，可以利用quartus软件直接运行-Design of FIR filter based on Verilog, the code contains a complete project, can use quartus software to run directly
account
- 一个电话计费器程序的实例，里面有文档说明相关信号的定义。-An example of a telephone billing procedures, there is documentation of the definition of the relevant signal.
clock
- 基于Verilog的多功能数字钟，看代码最好用quartus软件打开看。结合说明文档看。-Multi function digital clock based on Verilog, look at the code is best to use quartus software to open to see. Combined with the documentation see.
uart_fifo
- FPGA与PC的串口通信代码，使用了FIFO作为数据的缓存。-FPGA and PC serial communication code, use the FIFO as cached data.
8B10B
- 以太网PHY层中的组成部分 8B10B编码器-Part of the Ethernet PHY layer in 8B10B encoder
led
- LED呼吸灯硬件编程语言 Verilog 实现占空比变化LED灯缓慢点亮和熄灭的效果-LED Breathe
uart_8
- 用verilog描述的串口通信接口，主体为接收机和发送机两个模块-Serial communication interface with Verilog descr iption, subject to a receiver and transmitter module two