资源列表
Verilog-example3
- verilog实例分析第三部分，通过实例分析讲解有限状态机的设计过程。-The third case study verilog part, by an example to explain the finite state machine design process.
MastersThesisPreliminaryReport
- developmentof a reconfigurable muti-protocol verification environment using uvm methodology
tlm
- OSCI TLM 2.0 KIT UNIT TEST DEMO
convertermat
- Embedded applications have emerged appreciably during the past few years due to the considerable increase of nomad and traveller ways of life. These itinerant lifestyles induce the apparition and development of more and more portable and autono
matlabtoconver
- Embedded applications have emerged appreciably during the past few years due to the considerable increase of nomad and traveller ways of life. These itinerant lifestyles induce the apparition and development of more and more portable and autono
matlabtomodelsim
- matlab to model sim converter coding of vhdl code ypu want to convert that matlab into the xilinx platform model sim simulator
ldpc-code
- ldpc codes are low dencity paRity checking matrix to check the parity on matrix based g and h algorithm based on algorithm matrix input will be added to this code
ldpc-decoder-code
- Specify the decision method used for decoding as one of Hard decision | Soft decision . The default is Hard decision . When you set this property to Hard decision , the output is decoded bits of double or logical data type. When you set this property
UART
- （1）在FPGA上设计UART接收模块实现从PC接收串口数据(RS232串口通信)； （2）在FPGA上设计UART发送模块，把从PC接收的数据的16进制值加1再发送给PC； -(1) Design UART receiver module receives serial data (RS232 serial communication) the PC to the FPGA (2) Design UART transmit module on FPGA, the hexadecim
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度（芯片一般通过查表得到）。DDS芯片输出的一般是数字化的正弦波，因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
mpi
- MPI接口就是CPU和逻辑之间通信的一个接口，一般使用总线方式，总线一般有两种标准，一种是MOTO模式，另外一种是intel模式。-MPI interface is an interface for communication between the CPU and the logic, the general way of using the bus, the bus generally have two standards, one is MOTO mode, the other one i
flow_proc
- FPGA FLOW verilog流水线把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。以芯片面积换取时间，即面积换取频率-FPGA FLOW verilog To a complex pipeline logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal, increasing the frequency. The chip a