资源列表
COA_PRO
- 简单MIPS流水线指令集的verilog实现。初步实现了branch 的功能。-implement of Pipelined MIPS processor
DA0832_EDA
- DAC0832配套的一些VHDL程序语言，仅供大家学习！-DAC0832 some supporting VHDL programming language, only for them to learn!
verilog-up-counter
- Verilog code for 4 bit Sync Up Counter
verilog-lfsr-updown-counter
- Verilog 8 bit LFSR Up-Down Counter
verilog-8-bit-Gray-Counter
- Verilog 8 bit Gray Counter
Verilog-Divide-by-3-Counter
- Verilog Divide by 3 Counter
Verilog-Divide-by-45-Counter
- Verilog Divide by 4.5 Counter
1_hello
- fpga的nios hello程序，可快速了解fpga nios核的配置方法-fpga' s nios hello program, you can quickly learn how to configure fpga nios nucleus
9_timer
- fpga的nios timer程序，可快速了解fpga nios核的配置方法-fpga' s nios timer program, you can quickly learn how to configure fpga nios nucleus
led_demo
- fpga初始化，实现led流水灯实验，数码管计时，以及开发板各模块初始化-fpga initialize realize led light water experiments, digital timer, as well as the board of each module initialization
sclk_switch
- 在有些电路中需要时钟切换，比如某个电路支持高速模式和低速模式，在高速模式下系统工作在125M时钟，在低速模式下系统工作在3M时钟，在这样的设计中需要动态的将时钟从高频切换到低频，或者从低频切换到高频，切换过程可能会出现毛刺，是非常危险的，该程序能够有效的避免这个问题-Need some clock switching circuit, such as a circuit supports high-speed mode and low-speed mode, the system works i
flow_proc
- 流水线结构是在逻辑很复杂的情况下使用，通过分栈，把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。最形象的实例就是位宽较大的加法器。 把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。以芯片面积换取时间，即面积换取频率。-Pipeline structure is very complicated in the case of using the logic, through the sub-stack, to a complex logic is d