资源列表
DDS
- DDS的核心是相位累加器，相位累加器有一个累加器和相位寄存器组成，它的作用是再基准时钟源的作用下进行线性累加，当产生溢出时便完成一个周期，即DDS的一个频率周期。加载Matlab 产生的波形，通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under
SPI
- 一种基于FPGA，Verilog语言的SPI总线实现方式，顶层添加自己想要传输的内容到相应的地址就行，百分百可以。-Based FPGA, SPI bus implementations Verilog language, the top add your own content you want to transfer to the appropriate address on the line, can be hundred percent.
AD9362
- 一种基于xilinx S6，verilog语言，实现AD9362,IDDR ODDR接口的设计，已经过实际测试-Based xilinx S6, verilog language, achieve AD9362, design IDDR ODDR interface, has been the actual test
fir_noRom
- 有VHDL实现对复杂信号的16位fir滤波器-desgin the 16 bits FIR Filter by VHDL
tt
- python t_wave_53.py reads ../lena_256.png to generate m then reads lena256.hex writes test1_256_fwt.png and test1_256_iwt.png
signal-generator
- 进阶实验_16_DA[DA9708] ：输出正弦、方波、三角、锯齿(频率、幅度连续可调)-Advanced experimental _16_DA [DA9708] : output sine, square, triangle, sawtooth (frequency, amplitude adjustable)
keyboard-tube
- 进阶实验_09_PS2_02 ：接收标准键盘输入，显示在数码管-Advanced experimental _09_PS2_02: receiving standard keyboard input, displayed on the digital tube
MedianFilter33
- 基于3x3窗口的FPGA 调试好使的中值滤波程序,-Debugging that median filtering program
VGA
- 进阶实验_05_VGA ：通过VGA显示一个汉字，800X600@72Hz-Advanced experimental _05_VGA: through the VGA display a Chinese characters, 800 x600 @ 72 hz
1602
- 进阶实验_04_LCD1602显示 ：在LCD1602上显示RedCore网址-_04_LCD1602 advanced experiment shows: on the LCD1602 display RedCore url
Verilog-example1
- verilog实例讲解，经典例子分析，可以有效地帮助初学者入门。-verilog examples to explain, a classic example of the analysis, can effectively help beginners.
Verilog-example2
- verilog 实例讲解第二部分，进一步拓展对基础知识的应用，通过实例分析帮助大家理解verilog-verilog examples to explain the second part, to further expand on the basics of the application, by an example to help you understand verilog