资源列表
sdram
- vhdl 编写的sdram controler, 双通道
LZY
- 基于FPGA的软FIFO代码实现，双时钟，异步。VERILOG-FPGA-based soft FIFO code, two clocks, asynchronous. VERILOG
multi-cycle-MIPS
- multicycle-MIPS verilog implementation
D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
PS2
- 使用XLINX的FPGA实现P/S2的键盘接口
16_ps2_keyboard
- 基于NIOS II的键盘驱动设计设计，在FPGA平台上加入NIOS处理器以及需要的ip构成嵌入式系统实现键盘的控制-NIOS II keyboard-driven design-based design, and the need to join NIOS processor on an FPGA platform ip constitute embedded systems keyboard control
kp_uart
- This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
cordic_vhdl2
- 利用cordic实现三角函数的计算，用vhdl实现-use cordic achieve trigonometry calculations, using achieve vhdl
max5236
- a program for AD-Wandler max5236 in VHDL Language
Router
- 5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encoder-5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encode
pid_controler_latest.tar
- PID算法的VHDL程序，大家可以参考一下，同样有心得也可以发上来大家交流一下-PID algorithm of the VHDL program
rc5spartanboard
- rc5 encryption implementation using vhdl on spartan board-rc5 encryption implementation using vhdl on spartan board...