资源列表
washer
- 本人用verilog HDL写的一个洗衣机工作流程。由于是第一次写，难免很多不足~多多指教.-well ,this is a verilog project which describes a washer machine.
systemc
- 用新兴的硬件描述语言SYSTEMC编写的一个ALU功能单元-SYSTEMC programme
generator_2
- 一种新的正铉波发生器的实现源码。利用VHDL语言实现。有6个VHDL文件组成。其中generator 为顶层文件-A new realization of wave generator is Hyun source. Using VHDL language. There are six VHDL files. One generator for the top-level files
liushuideng
- S0 从左到右依次点亮 S1从右到左依次点亮 S2从两边到中间依次点亮 S3从中间到两边依次点亮-S0 S1 lit from left to right from right to left, light from both sides to the middle order S2 S3 light turn from the middle to both sides of the light
nios2_ch37x
- ch37x初始化，写命令，读命令，传输数据的nios2程序。-Ch372 initialization, read write command, command, nios procedures to transfer data
CapacityRAMModel
- Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
clock
- verilog 电子钟！！！ 用于初学者学习-Electronic clock design Electronic clock design Electronic clock design
watch
- 基于DE-2的数字跑表设计，并带两种显示功能-DE-2-based digital stopwatch design, with two display
baweianjiansaomiaodianlu-EDA
- 将成功的程序加载到相应的试验箱上面后，你按0--15中的任何数，在数码管上就显示出相应的数字 -The success of the program loaded into the appropriate chamber above, you press the 0- 15 in any number of the digital display on the corresponding figures
FIFO
- 此程序为verilog语言，实现的功能为FIFO功能，包括三个部分，分别实现不同的功能。-This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
chengxu
- 读取外部RAM的状态机 RAM接口OE，输出使能 WR，低电平写RAM AB【7：0】地址总线 DB【7：0】地址总线 //将RAM 0至127的数据读出并相加最后的结果存入地址254（低8位）255（高8位） -State machine reads the external RAM RAM interface OE Output Enable WR, low-level to write RAM AB [7:0] address bus DB [7:0
cepin
- 采用等精度测频原理实现较宽范围内频率的测量-With equal precision frequency measurement principle to achieve a wide range of frequency measurements