资源列表
web
- 模拟网络串行通信 近期对计算机间通信比较感兴趣，同时研究usb通信原理，起步为串行通信于是想为更好地理解其机理做一定基础性研究，故做了异步串行通信设计实验。 经过QUARTUS验证，获得了一等奖！-Simulation of the recent serial communication network between the communication of more interested in computers, communications usb at the same time
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
miaobiao
- 秒表功能，自带工程，EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
light
- 用vhdl语言实现交通灯控制，可以用quartus2软件打开并仿真，经本人仿真无误。-Vhdl language used to control traffic lights can be turned on and quartus2 software simulation, simulation accuracy, as I am.
alarm-clock
- 该代码用VHDL实现了闹钟的定时和提醒功能。里面包含四部分代码，分别实现了60，30，2分频；键盘控制；外围控制；用quartus2软件就可以打开，压缩包中附有四个代码的仿真结果。-The VHDL code used to achieve the alarm clock to remind the timing and function. Code which contains four parts, namely a frequency 60,30,2 keyboard control
Lattice-Machxo-FPGA-Loader
- Application note (source code + documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.-Application note (source code+ documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP progra
adder_n_bits
- vhdl entity adder of two words of nbits.
divisor_n_bits_sin_restauracion
- vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
lab8_wena_Arturo
- vga verilog code for showing the vga pattern and diferent functions for a Spartan develp card
LAB7
- Verilog code to move a servo.
cw
- 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的-signal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for alte