资源列表
ISP1362
- source code for ISP 1362
johnson
- JOHNSON计数器，8bit,在FPGA板子上简单的实现，给大家作为练习-JOHNSON counter
61EDA_D964
- 4_4小键盘扫描+VHDL语言的，可以实现数码管显示，有译码功能-Scan 4_4 small keyboard+ VHDL language can be achieved digital display, a decoding function
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
state
- 米勒解码器的状态转换模块。用verilog语言编写，ISE为开发环境-Miller decoder module of the state transition
suoxianghuan
- 这是一款计算锁相环参数的软件，附有源程序-This is a phase-locked loop parameters for the calculation software, with source code
glitch_gen
- Verilog產生glitch generator的範例-Verilog examples generated glitch generator
deb_dump_memory
- Verilog與debussy使用memeory的範例-Debussy using Verilog and the example of memeory
readmemb
- 在Verilog使用readmemb()函數範例-In Verilog use readmemb () function example
random
- Verilog使用$random()函數簡單範例-Verilog using the $ random () function of a simple example
diantikongziqi
- 电梯控制器的设计与分析.对电梯的控制过程进行VHDL语言描述。-Elevator controller design and analysis. On the elevator control process described in VHDL language.
Songer
- 用VHDL实现的一个简易音频播放器，非常实用的源代码-VHDL achieved with a simple audio player, a very useful source