资源列表
quartus_works_first
- 基于verilog语言的，FPGA程序，实现可暂停的计时器与数码管显示功能，计时范围0~99秒，精度0.01秒，在EP1C3T100C8上亲测通过-Based verilog language, FPGA program implementation can pause the timer with digital display function, time range from 0 to 99 seconds, precision 0.01 seconds, measured by the
int
- 通过按键中断来进行电平中断实验，本程序可以使用DEBUG模式进行在线调试-To carry out the experiment through the key level interrupt interrupted, the program can use DEBUG mode for online debugging
quartus_works_second
- 基于verilog语言的，FPGA程序，实现频率计与数码管显示功能，转换频率48M，精度1Hz，量程1Hz~9999Hz，有欠频率和超频率提示，精度与量程可随外部设备改变而改变，在EP1C3T100C8上亲测通过-Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 99
iic
- 使用的是FPGA单片机 通过IIC总线，对24LC04进行读写实验。写入512btye的数据，前256个数字为0到255，后256个数据为1。然后，将512byte数据读出来并打印。最后，对比数据是否相同，如果有不同，说明读写过程有错误-By using a single-chip FPGA IIC bus read and write on 24LC04 experiments. Write 512btye data, the first 256 digits from 0 to 255, a
flash
- 使用的是FPGA芯片 在NIOS II下进行FLASH实验； 实验内容： 向FLASH中写入100个数，然后再读取并打印出来。 -Using a FPGA chip FLASH experiment conducted under the NIOS II Experiment: The number 100 is written to FLASH, and then read and print them out.
QUARTUS_WORK_FORTH
- 基于verilog语言的，FPGA程序实现电脑与FPGA串口的数字传输，硬件设备为EP1C3T100C8，usb转RS232芯片为FT232BM，-Based verilog language, FPGA program FPGA serial digital transmission of computer and hardware devices to EP1C3T100C8, usb to RS232 chip FT232BM,
jpeg_encoder
- JPEG 编码器IP核，用verilog语言编写，不支持二级采样。-JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling
vhd4
- 用VHDL语言实现了FIFO_RAM，及先进先出储存器的实现。-Just like
third
- 用VHDL语言实现了一个有符号除法的程序，用移位相减实现。-Just like
vga controller vhdl de2
- vga vhdl altera de2 for vga screen
tugas-1
- Coding VHDL Substractor adder
jitter_filter
- Verilog按键消抖程序，根据按键时间进行消抖-Verilog key debounce program, according to the key debounce time