资源列表
rschufaqi
- 此程序是根据rs触发器的功能用VHDL语言描述的RS触发器，供同学们学习交流-This program is based on the RS flip-flop rs flip-flop functions described in VHDL language for students learning exchanges
jkchufaqi
- 此程序是根据jk触发器的功能用VHDL语言描写的jk触发器，供同学们学习交流-This program is based on the jk flip-flop functions with VHDL descr iption jk flip-flop for students learning exchanges
mendianlu
- 用VHDL语言描述了各种门电路，与门，或门，非门，与非，或非-VHDL language describes the various gates, AND gates, OR gates, NAND, NAND, NOR, etc.
liushuidengyouyi
- 此程序是用vhdl语言描写的流水灯程序，功能是流水灯左移-This procedure is used in light water vhdl language to describe the program, the function is left light water
quanjiaqi
- 此程序是用VHDL语言描写的全加器程序，从顶层开始设计的-This procedure is described using VHDL full adder program, designed to start from the top
doorlock
- 基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。-FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to
test_ddr2_ip
- ddr2 SDRAM 高性能控制器及测试-DDR2 SDRAM High Performance Controller
verilog
- 次doc文档中有ov7660摄像头模块的verilog驱动程序代码，可以实现对摄像头模块的驱动，实现摄像头的相应功能-There are times doc document verilog driver code ov7660 camera module, camera module can be achieved on the drive to achieve the corresponding functions of the camera
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
Dec_mul
- 时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我
edge
- fpga边沿中断检测程序，本程序可以用nios II 仿真。-fpga edge interrupt detection procedures, the procedures can be used nios II simulation.
rtc
- NIOS II下进行RTC实时时钟的开发,比较有难度的知识点： 1. PIO的深度应用； 2. C语言中函数指针的应用； 3. DS1302的驱动编写； 4. C语言中程序的模块化书写方式； -NIOS II development for the next RTC real time clock, have more knowledge of difficulty: . 1 PIO depth application 2 Application