资源列表
EDA
- EDA实验讲义GK 包含GW48 EDA系统使用说明以及许多实例。比如有时钟使能的两位十进制计数器原理图输入设计、用状态机对ADC0809的采样控制电路实现、硬件电子琴电路设计-EDA experimental GK notes GW48 EDA system contains, as well as many examples of use. For example, there are two clock-enabled input decimal counter schematic des
4multiplier
- 4位乘法器vhdl程序-- DEscr iptION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
shujujiegou
- 数自逻辑实验报告有关于83译码器的编写，用VHDL编写程序-Since the logic of the report of the number of experiments on the preparation of 83 decoder using VHDL programming
srff
- SR flip flop is implemented using VHDL
jkff
- JK flip-flop is implemented using VHDL
mux
- Mulriplexer is implemented using VHDL.
vhdl
- full adder is implemented using VHDL
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
74LV245
- VHDL语言是面向硬件的语言，非常重要的文件-VHDL language is the language of the hardware-oriented
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog