资源列表
The_Verilog_Golden_Reference_Guide
- Verilog golden reference guide
FPGA
- 基于FPGA的直接数字频率合成器的设计和实现.采用DDS频率合成技术。-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation. Using DDS synthesizer technology.
NIOSII-Step-by-step
- FPGA中有关niosii的，对初学者很有用的文档。-Niosii relating to the FPGA, and the document is useful for beginners.
CPLDFPGAGuide
- CPLD_FPGA高级应用开发指南,适合学习-Advanced Application Development Guide CPLD_FPGA for learning
lift
- 电梯控制程序，按钮控制电梯的上下，拨玛开关设置楼层。-Elevator control procedures of the upper and lower elevator button control, set the dial switch floors Ma.
Splitter
- Splitter file to be used to split altera avalon st video stream into two avalon st streams.
HDB3
- VHDL语言编写的HDB3码的编译码模块-VHDL language code HDB3 codec module
S3E_Ethernet
- acces to send the data on the internet
qumaoci
- 关于FPGA设计中去毛刺的方法。有各种文档和论坛言论，很有参考价值-On the FPGA design methodology deburring. There are various documents and forums of speech, of valuable
wireless
- 无线通信模块FPGA实现。可以先来看看，共参考，大家分享。-FPGA realization of wireless communication module. Can first take a look at a total of reference to share with you.
prac2
- VHDL implementation using mouse and monitor
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica