资源列表
altfp_mult_DesignExample_ex
- 浮点数乘法 verilog语言编写 可直接调用-Floating-point multiplication verilog language
altfp_log
- 浮点数 log运算模块 verilog语言编写 可直接调用-Log floating point arithmetic module can directly call verilog language
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
altfp_matrix_mult
- 浮点数 矩阵乘法模块 verilog语言编写 可直接调用-Floating-point matrix multiplication module can directly call verilog language
nixietubenew
- FPGA片上运动计时器实现，使用数码管显示计时，包含暂停与重置-Movement on the FPGA chip timer implementation, use digital display timing, including pause and reset
and2.nand2-.or2
- 二输入与门、或门、与非门VHDL代码描述-Two-input AND gates, OR gates, NAND gate VHDL code descr iption
Calculator
- 4位十进制计算器，有加，减，乘，除四个功能，并有检测代码。-4bit decimal computers, there are add, subtract, multiply, divide four function, and detection code.
am
- 利用altera的cyclone FPGA芯片，实现AM调制，并使用自带的逻辑分析仪仿真成功。-The use altera cyclone FPGA chip, AM modulation, and use its own logic analyzer successful simulation
dds
- 利用altera的cyclone FPGA芯片，模拟DDS原理，产生频率可调的正弦波，并使用自带的逻辑分析仪仿真成功-The use altera cyclone FPGA chip, analog DDS principle, have adjustable frequency sine wave, and use the built-in logic analyzer simulation success
fm
- 利用altera的cyclone FPGA芯片，实现FM调制，并使用自带的逻辑分析仪仿真成功-The use altera cyclone FPGA chip, FM modulation, and use its own logic analyzer successful simulation
fpga_qpsk_fsk
- 采用TI的DSP6713协同ALTERA的FPGA芯片实现数字qpsk和FSK调制,并仿真测试成功-TI s DSP6713 collaborative ALTERA FPGA chip digital qpsk and FSK modulation and simulation test was successful.
fm(912)
- 利用altera的FPGA，采用DDS原理实现FM调试，调试系数可改变，并通过DA变换输出，仿真以及下板测试成功-The use altera FPGA, using the DDS principle to achieve FM debugging, debugging coefficient can be changed through DA conversion output, simulation, and the lower plate test is successful