资源列表
adc_30hz
- VHDL内部RAM+1KHZ+480点压缩算法+找最大值-VHDL internal RAM+1 KHZ+480 points to find the maximum compression algorithm+
top.tar
- 用verilog寫出來的貪食蛇程序,使用開原軟體iverilog進行摹擬-a simple program written in verilog
itrl
- 交织 本程序是自己编写的随机交织 可以实现任意维度 任意长度 的交织 比起其他的实现方法更具有 推广型-Intertwined in this program is to prepare its own random interleaving can achieve any arbitrary length of the intertwined dimensions of the implementation is more than the other type has the ext
FPGA---Serial
- FPGA实现的串口程序，包含顶层调用的代码。-FPGA implementation of the serial program, including top-level calling code.
FIFO
- 本文件包含仿真文件和工程文件，完成的功能是实现FIFO。-This file contains the simulation files and project files, complete function is to achieve FIFO.
pi_li_deng
- pic mplab环境下的软件 安装在目标板上 霹雳灯-PIC MPLABASM MPLABICD
vhdl_miaobiao
- 用vhdl实现秒表的功能，具有秒表功能,有分、秒显示，后期可以自己添加闹钟的模块。 -Use VHDL to achieve the functions of a stopwatch with a stopwatch function, who, seconds indicates that the latter can add their own alarm clock module.
32×4bitRAM
- 32×4bit 的RAM设计。VHD语言。能在ISE上仿真。
用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
UART
- verilog实现UART，分模块实现，希望对大家有所帮助-verilog-- UART
tdc
- 线性伸展TDC的verilog，包含门级网表-TDC linear stretch of verilog, includes gate-level netlist