资源列表
clock
- 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
DDSpro
- DDS技术的设计代码，利用quartus II编写，供大家参考-DDS technology design code
VHDL
- 分块地址产生电路，根据FPGA的要求，按照存储模块分块管理的要求产生电路-Block address generating circuit according to the requirements of FPGA, the memory module according to the requirements of the management block generating circuit
287eb141911b
- 用VHDL编写的usb控制器，能实现usb的读写控制及片选。-Prepared using VHDL usb controller, usb reading and writing to achieve control and chip select.
RS_decoder
- Reed solomon decoder based on table-lookup method VHDL code
voice-read-and-write-program
- this a voice read and write program using c language.-this is a voice read and write program using c language.
efuse_ctrl
- E-fuse controller for TSMC 0.16um
sd
- 计算海平面的对应的ssh对应的数据源是海洋数据-compute shh
src
- 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
spi_1
- 主要是描述SPI接口的源代码，希望能给大家带来帮助。-SPI interface is described in the source code, I hope we can help.
uart_verilog
- UART Verilog，书中里的例子，绝对正确，用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginn
PWM_contro__
- DC12v转AC30V-90V-250V PWM脉宽调制电源主程序-DC12v turn AC30V-90V-250V PWM pulse-width modulated power supply main