资源列表
LCD1602
- 实现LCD控制之下六位时钟正确计数与显示-Realized under the control of six LCD clock display correctly count
8-bit-CPU
- This is a simple 8-bit CPU verilog source code,which includes user s guide.
CLA4
- Carry look a head adder Verilog
Booth4b
- booth 4 bits programmed by verilog and simulated using ISE software and no implemented
cdkz
- 主要实现八个彩灯控制，八种花样变化，循环转换，四种不同频率。-control eight lights,change eight form
spi
- SPI的Verilog实现，好用的代码。-SPI Verilog implementation, good code.
crc
- 基于verilog的CRC算法-CRC algorithm based on verilog.
fsm
- 三段式状态机的典型写法，verilog实现-The three section type of typical state machine method, Verilog implementation
pipeline
- 简单的流水线的实现机制，基于verilog语言。-The pipelined implementation, based on Verilog language.
rom
- ROM模式的实现机制，基于verilog语言。-Implementation mechanism of ROM model, based on Verilog language.
FPGA-Read-or-Write-CF
- 利用ALTERA FPGA实现对CF的读写操作-Using ALTERA FPGA implementation of CF, speaking, reading and writing operations
VerilogPHDL
- Verilog及其VHDL相应的代码风格和各种实例，包括夏宇闻书中的全部源代码-code style of Verilog and vhdl