资源列表
CJQ-V1.0-fpga
- 主要实现采集电网信号的功能，源码包括控制AD7606进行AD转换，其次实现FT3数据的传输，包括转为曼彻斯特编码-Collecting grid signal to achieve the main function, including control of AD7606 source for AD conversion, followed by the realization of FT3 data transmission, including to Manchester encoding
i2c_master_slave_core
- I2C master/slave IP core
CLock
- 电子时钟VHDL实现，包括调整时间，闹钟功能-Digitai clock based on FPGA in VHDl
I2C-Master-_-Slave-Core
- 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
IEEE_Verilog_2001
- 原版IEEE verilog/VHDL 2001标准。-IEEE verilog/VHDL 2001
VHDL_lecture_notes_-_NAVABI
- VHDL lecture notes by Navabi
BJ-EPM240_study_guide_plate
- BJ-EPM240V2实验例程以及说明文档实验之BJ-EPM240学习板使用指南-BJ-EPM240V2 experimental test routines as well as documentation of the BJ-EPM240 study guide plate
uart
- 用verilog写的程序实现串口通信， 用verilog写的程序实现串口通信， -the program is based on verilog, and it s fuction is comunicate with uart
Pico_Blaze_sources_VHDL
- Some useful PicoBlaze sources.
NIOSIIREV[1].0.2
- 一个很不错的学习FPGA NIOSII学习资料-A very good learning materials learning FPGA NIOSII
base-on-FPGA-AES-addkey-design
- 介绍了用FPGA实现AES算法所用的开发工具，开发语言和所选用的芯片，及AES算法的硬件实现方式。着重阐述了AES算法FPGA实现的总体设计框图，并副有部分源代码- introduce design tool,language and core of AES which base on FPGA,and AES hardware design.
Mars_EP1C3_S_Core_V2.0
- 此包中为Mars_EP1C3_S_Core_V2.0 FPGA学习板中的接口实验代码.共包括10个实验源代码:7段数码管,i2c,KEYSCAN,MCU,PS2,UART,VGA，蜂鸣器，跑马灯和拨码开关. -This learning package for Mars_EP1C3_S_Core_V2.0 FPGA board interface test code. A total of 10 experiments, including source code: 7 segment di