资源列表
RobustVerilog_free1.2_win
- RobustVerilog生成verilog工具-RobustVerilog version
MTC700_VGA.RAR
- VGA Code for an spartan 3e in vhdl with an ucf file. You will find everything in de zip
ADC1
- 关于A/D的模拟到数字的转换，通过大家熟悉的Verilog语言实现。-On the A/D conversion of analog to digital by the familiar Verilog language.
LCD1602_controller
- 基于VHDL的LCD 1602 控制器源程序，Altera cyclone II 系列-The source program of LCD 1602 controller
1_lab1
- （1）熟悉S6 CARD实验板； （2）熟悉ISE集成开发环境； （3）3比特加法器仿真与上板实验； （4）m序列产生器仿真与在板Chipscope调试 -(1) be familiar with the S6 CARD experimental board (2) be familiar with ISE Integrated Development Environment (3) 3-bit adder simulation experiment on board (4
altera_inspector.log
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
DE2_Web_Server
- ALTERA DE2開發板一個網路晶片DM9000A的應用範例 並將一個網頁嵌入到DE2開發板中
shiyan8
- 出租车计费系统verilog hdl编写-verilog hdl taxi
DE2_Web_Server
- 此文件是altera公司发布的基于DE2开发板的-web例程，能实现DE2开发板与计算机之间的信息传输，采用vhdL语言编写。-This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.
mips
- in verilog 8bit mips processor
Archive
- FPGA Basics FPGA coding
CPLD-Three-voting
- CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voti