资源列表
clock
- XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the
state
- 状态机程序，具有简易功能的自动贩卖机verilog hdl-Program of the state machine, vending machine with a simple function verilog hdl
ws
- 矩阵变换器换流部分的程序，写的有点多，用的是电压型换流方法，欢迎多交流。-Matrix converter commutation part of the program, write a bit more voltage type converter to welcome more exchanges.
spi
- this the SPI slave module -this is the SPI slave module
design
- 基于cycloneII系列FPGA实现信号等精度测量频率、相位、周期-Realization precision measurement frequency, phase, period
sdram_control
- 基于FPGA对sdram控制器的设计（VERILOG语言）-sdram fpag verilog
sdram_control
- 基于硬件语言Verilog的一个sdram控制器的设计以及仿真-Verilog language, a hardware-based controller design and simulation sdram
multiplier_ip
- 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
T4_sdram_control
- 红色飓风的EP2C20开发板的关于sdram操作的详细资料，里面有说明文档和例程分析。-Red Hurricane EP2C20 development board on the sdram details of the operation, which has made it clear documentation and routine analysis.
wisbone_2_ahb.tar
- ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Descr iption ---- ---- Implementation of Wishbone_
wisbone_2_ahb.tar
- ARM Bus Interface RTL Reference Code
FPGA_fenpin
- 利用FPGA构建一个1:1的分频器，稍加修改即可改成频率可控获占空比可控的时钟输出。-Using FPGA to build a 1:1 divider, you can change the frequency slightly modified controllable duty cycle controlled by the clock output.