资源列表
sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
shuzizhong
- Verilog写成的数字钟 可以在ISE或者quartus环境下运行仿真-Verilog digital clock can be written in the ISE environment or running simulation quartus
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
sopc_uart_rt
- sopc的一个应用例程：应用uart部件搭建的一个sopc系统，调试成功了。包含所有源代码-An application of routine sopc: Application uart component erected a sopc system, commissioning a success. Contains all the source code
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
quartusii10.1_handbook
- altera公司退出的最新quartusii10.0的手册，使用说明。-The latest company to exit quartusii10.0 altera manuals, instructions for use.
beep
- verilog写的控制喇叭的FPGA程序。-written in Verilog FPGA speaker control procedures.
CVBS
- CVBS，用于生成模拟视频信号，NTSC/PAL可选-CVBS Signal Generator，NTSC/PAL could be selected
jow_order
- 这是我准备电子设计大赛时，用VHDL写的一个自动打铃系统，很好的学习资料。-This is when I am going to Electronic Design Contest, use VHDL to write an automatic bell playing system, a very good learning materials.
VHDLLPM
- 应用vhdl语言，调用lmp块，非常有用，电子类设计必备-Application vhdl language, called lmp block, very useful, necessary electronic design
tPad_Camera
- tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。-tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such
CCD-driver
- CCD芯片驱动VHDL程序，CCD型号TC253SPD -CCD chip driver VHDL program, CCD models TC253SPD