资源列表
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
aurora_ipcore_dir
- xilinx v5下面，一个基于aurora通信的实现代码-implement of aurora in xilinx
xilnx_sata
- xilinx 的sata解决方案，已对其中内容作了修改，可实现综合-sata the xilinx solutions have been made to amend the contents of which can be used
DSSS
- 基于FPGA的我直接扩频序列发射机的quarters代码，-direct sequence transmitter
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
XILINX_ML505_REVA_ASSY_110306
- XILINX公司的ML505开发板参考设计源码打包-XILINX
SystemverilogSource
- systemverilog程序，需要的朋友可以参看-SystemVerilog procedures need friends can see
fsm
- VHDL新手入门：有限状态机练习（三段式结构）-VHDL Getting Started: Finite state machine exercises (three-stage structure)
xilinxusb
- xilinx USB 下载线资料与程序, -xilinx USB download cable data and procedures, many money to buy the
ug_ram
- RAM design for FPGA in verilog
FPGA-RAM-Verilog
- 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
vhdlad
- 基于VHDL的高速串行AD转换器控制设计与实现-VHDL-based high-speed serial AD converter control design and implementation