资源列表
Senior-Advanced-FPGA-design
- FPGA设计高级进阶，讲述了流水线，乒乓操作，异步时钟域处理，状态机等内容-Senior Advanced FPGA design, about the line, ping-pong operation, asynchronous clock domain processing, state machine, etc.
collect
- 用verilog编写的max197这个AD转换的程序，在ISE综合仿真均通过。-max197, verilog
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
ramFIFO
- 双口RAM实现FIFO程序解释,说明.-FIFO dual-port RAM procedures to achieve explanation. Good
counter_3
- 三种计数器的verilog实现,二进制计数器,格雷码计数器,约翰逊计数器.初学硬件描述语言可参考。-Three kinds of counter verilog implementation of a binary counter, gray code counter, Johnson counter beginner hardware descr iption language can refer to
DE2_70
- DE2-70 入门实验，非常不错的入门指导书-DE2-70 Introduction to experimental, very good introductory guide book
Hardware_Multiplier
- 用VHDL写的硬件乘法器，以及测试过了，一个时钟周期内完成乘法运算。被乘数、乘数的宽度通过通用属性GENERIC参数改变而轻松改变，硬件除法器也快好了。-Written by VHDL hardware multiplier, and tested, and a clock cycle multiplication. Multiplicand, multiplier width parameter changes through the common property of GENERIC an
dpram
- FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
qpsk
- qpsk调制解调的FPGA实现。QPSK为调制程序，QPSK-two为解调程序。-qpsk modulation and demodulation of the FPGA. QPSK as the modulation process, QPSK-two for the demodulation process.
verilog
- 用Verilog语言描述比较器,数据选择器-Verilog language used to describe comparators, data selector
key_xiaodou
- 该资料是用vhdl编写的按键消抖程序，按键消抖在使用按键的数字电路中非常重要，如果不对按键信号进行处理，有可能会出现大量错误的按键信号。文件key_xd.vhd是按键消抖程序，文件key_xd.vwf是仿真波形文件。该程序已经通过仿真测试，并且在电路板上调试通过，效果理想。-The information is written in the key consumer vhdl shaking procedures, key consumer shaking in digital circuits