资源列表
HUAWEI_FPGA
- 华为内部资料，华为FPGA全套资料，包括华为的专利设计-Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design
MPDU_ASSEMBLER
- G.hnMAC层功能代码，实现了MPDU的资源调度-G.gn MAC codeG.gn MAC codeG.gn MAC code
bubblesort1024ram
- 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking trad
music_ok
- 简单的通过FPGA控制蜂鸣器播放音乐程序（verilog 源码）-Through the FPGA to control the buzzer play the music program (Verilog source code)
VHDL-SPI-Module.doc
- 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmit
i2s_to_parallel
- wm8731音频采集芯片的I2S采集时序的vhdl实现。-wm8731 I2S audio capture chip timing acquisition vhdl implementation.
MIPS_CPU
- 一个完整的MIPS CPU的设计，是创新设计项目，内含详细的项目设计报告-A complete MIPS CPU design, innovative design projects, detailed project design report containing
trafficlight
- 已应用在北京某校园内的交通灯控制程序，可以自动控制，手动控制，可以输入设定时间等等。verilog源代码-Has been used in a Beijing campus traffic light control procedures can be automatic, manual control, you can enter the set-up time, etc.. verilog source code
part01
- 周立功嵌入式系统实验教程中配带光盘资料，共分五部分-Ligong week experimental course in embedded systems equipped with CD-ROM, is divided into five parts
gequ
- 梁祝歌曲，用vhdl语言实现，在蜂鸣器上实现唱歌功能-Butterfly song
CPU
- 用VHDL设计的cpu 用微指令方法设计 通过rom查表的方式进行设计-Cpu design with VHDL designed by microinstructions way through the design of look-up table rom
hdlc
- 基于FPGA的HDLC协议控制器，能完成插零，删除0操作。-HDLC controller base on FPGA