资源列表
delay_line
- 延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module
Elevator_controller
- 电梯控制器VHDL程序与仿真,程序注释详细，可读性强。-Elevator controller and simulation of VHDL program, the program notes in detail, strong readability.
DDS_VERILOG
- verilog dds 在发生正弦波时，很好的参考代码-verilog dds
lanqiujishiqi
- 这是篮球计时器，vhdl源代码，包括12min倒计时，24sec倒计时-basketball game time paly.including 12min，24sec……
chessboard_vga
- Chessboard Pattern using Spartan 3e
fudianshuyunsuan
- 介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
small_fifo
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小，易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand
tftdot
- 我用verilog hdl写的tft lcd屏的控制程序，用来点亮屏上的任意点-I write the program in verilog hdl,it is used to control the tft lcd
利用LABVIEW实现板卡数据读取和发送
- 利用LABVIEW实现板卡数据读取和发送，此程序为主界面程序-labview
lift
- 设计一个八层楼房自动电梯控制器，用八个 LED显示电梯行进过程，并有数码管显示电梯当前所在楼层位置，在每层电梯入口处设有请求按钮开关，请求按钮按下则相应楼层的LED 亮。 -Design a controller, eight-story buildings, escalators, moving elevator with eight LED display process, and a digital display where the floor lift the current loc
dff_pre_clr
- 带置复位的D触发器的Verilog描述和仿真波形。-Reset the D flip-flop with set of Verilog descr iption and simulation waveforms.
stopwatch
- 此程序实现计时秒表功能，时钟显示范围00.00～99.99秒，分辨度:0.01秒 采用PIC16F877单片机，6位数码管显示 开发平台：MPLAB IDE v8.30 类型：工程文件（内有C源码），已验证通过-This program achieved stopwatch function, clock display range 00.00 to 99.99 seconds Resolution: 0.01 seconds using PIC16F877 microcontro