- Jot This a jot Project. have a try and enjoy it. Hope it helps
- ACP3 this acp is even more simple
- baomingcheng 一个报名程序
- java Java的一些入门级代码
- floating-car 城市浮动车数据参考资料
- ops-loongson2 We can t address 8 and 16 bit words directly. Instead we have to read write a 32bit word and mask modify the data we actually want.
资源列表
zigbee_sensor
- ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear qua
music_1
- 这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐 -This is a Quartus II software in the preparation of the VHDL program. After the buzzer can be used to download music player
wannianli
- 采用VHDL语言编写的万年历程序，可在液晶上显示！-Using VHDL language calendar procedures, can be displayed on the LCD!
mydesign
- FPGA实现简易数字频率计设计。自己设计，绝对原创-FPGA realization of simple digital frequency meter design. Their own design, an absolute original
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
32_16div
- 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
8-bit
- 最基本的vhdl運算，採用8bit作乘法器，將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
cis_100dpi_dsp
- 程序实现了采用CIS+AD9822+FPGA的结构形式对人民币进行采集。然后把采集到得数据通过EMIF接口传送给DSP。已通过调试-Program implements the use of CIS+ AD9822+ FPGA structure in the form of the RMB is collected. Then the data collected was transmitted through the EMIF interface to the DSP. Has passed
NiosII_clock
- 用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
alu
- 用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能-Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right
FPGA-DE1-PACMAN
- Pacman 4 DE1-FPGA-Board