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文件名称:mydesign

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    2012-10-28
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FPGA实现简易数字频率计设计。自己设计,绝对原创-FPGA realization of simple digital frequency meter design. Their own design, an absolute original
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下载文件列表

mydesign/.untf
mydesign/automake.log
mydesign/bitgen.ut
mydesign/COUNT10.ana
mydesign/count10.bgn
mydesign/count10.bit
mydesign/COUNT10.bld
mydesign/COUNT10.cmd_log
mydesign/COUNT10.dly
mydesign/count10.drc
mydesign/COUNT10.jhd
mydesign/COUNT10.ldo
mydesign/COUNT10.mrp
mydesign/COUNT10.nc1
mydesign/COUNT10.ncd
mydesign/COUNT10.ngc
mydesign/COUNT10.ngd
mydesign/COUNT10.ngm
mydesign/COUNT10.ngr
mydesign/COUNT10.pad
mydesign/COUNT10.par
mydesign/COUNT10.pcf
mydesign/COUNT10.prj
mydesign/COUNT10.spl
mydesign/COUNT10.sprj
mydesign/COUNT10.stx
mydesign/count10.sym
mydesign/COUNT10.syr
mydesign/COUNT10.twr
mydesign/COUNT10.twx
mydesign/COUNT10.ut
mydesign/COUNT10.v
mydesign/COUNT10.xpi
mydesign/COUNT10_map.ncd
mydesign/COUNT10_map.ngm
mydesign/COUNT10_ngdbuild.nav
mydesign/CP.v
mydesign/CP1.ana
mydesign/cp1.bgn
mydesign/cp1.bit
mydesign/CP1.bld
mydesign/CP1.cmd_log
mydesign/CP1.dly
mydesign/cp1.drc
mydesign/CP1.jhd
mydesign/CP1.ldo
mydesign/CP1.mrp
mydesign/CP1.nc1
mydesign/CP1.ncd
mydesign/CP1.ngc
mydesign/CP1.ngd
mydesign/CP1.ngm
mydesign/CP1.ngr
mydesign/CP1.pad
mydesign/CP1.par
mydesign/CP1.pcf
mydesign/CP1.prj
mydesign/CP1.spl
mydesign/CP1.sprj
mydesign/CP1.stx
mydesign/cp1.sym
mydesign/CP1.syr
mydesign/CP1.twr
mydesign/CP1.twx
mydesign/CP1.ut
mydesign/CP1.v
mydesign/CP1.xpi
mydesign/CP1_map.ncd
mydesign/CP1_map.ngm
mydesign/CP1_ngdbuild.nav
mydesign/CP2.ana
mydesign/cp2.bgn
mydesign/cp2.bit
mydesign/CP2.bld
mydesign/CP2.cmd_log
mydesign/CP2.dly
mydesign/cp2.drc
mydesign/CP2.jhd
mydesign/CP2.ldo
mydesign/CP2.mrp
mydesign/CP2.nc1
mydesign/CP2.ncd
mydesign/CP2.ngc
mydesign/CP2.ngd
mydesign/CP2.ngm
mydesign/CP2.ngr
mydesign/CP2.pad
mydesign/CP2.par
mydesign/CP2.pcf
mydesign/CP2.prj
mydesign/CP2.spl
mydesign/CP2.sprj
mydesign/CP2.stx
mydesign/cp2.sym
mydesign/CP2.syr
mydesign/CP2.twr
mydesign/CP2.twx
mydesign/CP2.ut
mydesign/CP2.v
mydesign/CP2.xpi
mydesign/CP2_map.ncd
mydesign/CP2_map.ngm
mydesign/CP2_ngdbuild.nav
mydesign/CTR.ana
mydesign/ctr.bgn
mydesign/ctr.bit
mydesign/CTR.bld
mydesign/CTR.cmd_log
mydesign/CTR.dly
mydesign/ctr.drc
mydesign/CTR.jhd
mydesign/CTR.ldo
mydesign/CTR.mrp
mydesign/CTR.nc1
mydesign/CTR.ncd
mydesign/CTR.ngc
mydesign/CTR.ngd
mydesign/CTR.ngm
mydesign/CTR.ngr
mydesign/CTR.pad
mydesign/CTR.par
mydesign/CTR.pcf
mydesign/CTR.prj
mydesign/CTR.spl
mydesign/CTR.sprj
mydesign/CTR.stx
mydesign/ctr.sym
mydesign/CTR.syr
mydesign/CTR.twr
mydesign/CTR.twx
mydesign/CTR.ut
mydesign/CTR.v
mydesign/CTR.xpi
mydesign/CTR_map.ncd
mydesign/CTR_map.ngm
mydesign/CTR_ngdbuild.nav
mydesign/DIS.ana
mydesign/dis.bgn
mydesign/dis.bit
mydesign/DIS.bld
mydesign/DIS.cmd_log
mydesign/DIS.dly
mydesign/dis.drc
mydesign/DIS.jhd
mydesign/DIS.ldo
mydesign/DIS.mrp
mydesign/DIS.nc1
mydesign/DIS.ncd
mydesign/DIS.ngc
mydesign/DIS.ngd
mydesign/DIS.ngm
mydesign/DIS.ngr
mydesign/DIS.pad
mydesign/DIS.par
mydesign/DIS.pcf
mydesign/DIS.prj
mydesign/DIS.spl
mydesign/DIS.sprj
mydesign/DIS.stx
mydesign/dis.sym
mydesign/DIS.syr
mydesign/DIS.twr
mydesign/DIS.twx
mydesign/DIS.ut
mydesign/DIS.v
mydesign/DIS.xpi
mydesign/DIS_map.ncd
mydesign/DIS_map.ngm
mydesign/DIS_ngdbuild.nav
mydesign/LAT.ana
mydesign/lat.bgn
mydesign/lat.bit
mydesign/LAT.bld
mydesign/LAT.cmd_log
mydesign/LAT.dly
mydesign/lat.drc
mydesign/LAT.jhd
mydesign/LAT.ldo
mydesign/LAT.mrp
mydesign/LAT.nc1
mydesign/LAT.ncd
mydesign/LAT.ngc
mydesign/LAT.ngd
mydesign/LAT.ngm
mydesign/LAT.ngr
mydesign/LAT.pad
mydesign/LAT.par
mydesign/LAT.pcf
mydesign/LAT.prj
mydesign/LAT.spl
mydesign/LAT.sprj
mydesign/LAT.stx
mydesign/lat.sym
mydesign/LAT.syr
mydesign/LAT.twr
mydesign/LAT.twx
mydesign/LAT.ut
mydesign/LAT.v
mydesign/LAT.xpi
mydesign/LAT_map.ncd
mydesign/LAT_map.ngm
mydesign/LAT_ngdbuild.nav
mydesign/mydesign.npl
mydesign/mydesign.ptf
mydesign/testbench.cmd_log
mydesign/testbench.prj
mydesign/testbench.sprj
mydesign/testbench.syr
mydesign/TOP.ana
mydesign/top.bgn
mydesign/top.bit
mydesign/TOP.bld
mydesign/TOP.cel
mydesign/TOP.cmd_log
mydesign/TOP.dly
mydesign/top.drc
mydesign/TOP.jhd
mydesign/TOP.ldo
mydesign/TOP.mrp
mydesign/TOP.nc1
mydesign/TOP.ncd
mydesign/TOP.ngc
mydesign/TOP.ngd
mydesign/TOP.ngm
mydesign/TOP.ngr
mydesign/TOP.pad
mydesign/TOP.par
mydesign/TOP.pcf
mydesign/TOP.prj
mydesign/TOP.spl
mydesign/TOP.sprj
mydesign/TOP.stx
mydesign/top.sym
mydesign/TOP.syr
mydesign/TOP.tf
mydesign/TOP.twr
mydesign/TOP.twx
mydesign/TOP.ucf
mydesign/TOP.ucf.untf
mydesign/TOP.ut
mydesign/TOP.v
mydesign/TOP.xpi
mydesign/TOP_last_par.ncd
mydesign/TOP_map.ncd
mydesign/TOP_map.ngm
mydesign/TOP_ngdbuild.nav
mydesign/transcript
mydesign/vish_stacktrace.vstf
mydesign/vsim.wlf
mydesign/_impact.cmd
mydesign/_impact.log
mydesign/__projnav.log
mydesign/work/_info
mydesign/work/@c@o@u@n@t10/verilog.psm
mydesign/work/@c@o@u@n@t10/_primary.dat
mydesign/work/@c@o@u@n@t10/_primary.vhd
mydesign/work/@c@p1/verilog.psm
mydesign/work/@c@p1/_primary.dat
mydesign/work/@c@p1/_primary.vhd
mydesign/work/@c@p2/verilog.psm
mydesign/work/@c@p2/_primary.dat
mydesign/work/@c@p2/_primary.vhd
mydesign/work/@c@t@r/verilog.psm
mydesign/work/@c@t@r/_primary.dat
mydesign/work/@c@t@r/_primary.vhd
mydesign/work/@d@i@s/verilog.psm
mydesign/work/@d@

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