资源列表
VerilogHDL-tutorial
- VerilogHDL硬件描述语言教程，较详细的介绍了verilog的基本用法-VerilogHDL hardware descr iption language tutorial, more detailed introduction to the basic usage of verilog
Verilog-HDL-
- 关于Verilog HDL的介绍。包括Verilog hdl的发展历史，语法应用介绍-On the Verilog HDL descr iption. Including Verilog hdl history of development, syntax described applications
spacewar_final
- 一款用VHDL编写的飞机大战游戏很好很实用-a game by VHDL
AES128
- AES128 encription vhdl code
Architecture
- clock divider in XILINX
60jishuqi (2)
- 这是一个可以记到60的计数器，可用于数字钟层次化设计。(This is a counter that can be recorded to 60, and can be used for the hierarchical design of digital clock.)
Assertion_based_Design_2nd
- Verilog HDL 语言设计的书籍，用IC设计门类，关于阻塞-Verilog HDL, design books, with the IC design categories, on the block
led_yiwei
- 基于Verilog语言的移位法的流水灯设计，持续运行长时间，易于理解。-Verilog language of light water displacement method based on continuous operation for a long time, easy to understand.
diver
- 根据芯片的始终频率进行分频，可调节占空比。容易实现。(The frequency division is carried out according to the chip frequency at all times, and the duty cycle is adjusted. Easy to implement.)
new_2ask
- 做课程设计时写的，关于2ASK的调制和解调，里面代码测试过，完好-Do curriculum design written about 2ASK modulation and demodulation, which tested the code, intact
key_test(4x4)
- FPGA扫描4*4按键，采集按键信息并通过LED显示-FPGA scan 4*4 keys,displayed be LEDs
TLC5510
- VHDL实现对TLC5510的控制，带有signaltap仿真图-VHDL implementation of the TLC5510 control, with signaltap simulation diagram