资源列表
xilinx_edk_9.2_crack
- xilinx edk 9.2 破解器/注册机-xilinx edk 9.2 crack
EP1C6Q240C6
- EP1C6Q240C6开发板原理图，自己做的FPJA 和大家分享一下-EP1C6Q240C6 development board schematics, myself and share with you the FPJA
rotary
- Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序-Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light
liushun
- 流水灯和跑马灯的程序 已经编译 可以用 是quartus的开发环境-Marquee lights and running water has been the procedure can be used to compile the development environment is quartus
VHDL_logic_v3
- Altera USB-BLASTER 源码-Altera USB-BLASTER source
XilinxISE9.2andChinpScopePro9.2Sn
- Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
atan
- 自己写的cordic 的 64位计算反正切的程序，-cordic count atan program
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
lvpecl_connect_lvds
- 在FPGA间实现LVDS和LVPECL互联时的用法，比如如何做匹配网络-Achieved in the FPGA LVDS and LVPECL interconnection between the time of usage, such as how to do the matching network
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
lift-verilogHDL
- 利用verilog语言实现一个简单的电梯控制，可借助最小系统开发板进行试验-control lift by using verilong HDL
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising