资源列表
spartan6_ibis
- Xilinx Spartan-6 FPGA 信号完整性 分析仿真模型(Xilinx, Spartan-6, FPGA signal integrity Analytical simulation model)
CycloneIII_EP3C40F780C8_26_DDRII
- SOPC,CycloneIII系列芯片EP3C40F780C8,NIOS II IDE,DDR II测试实验代码-SOPC,CycloneIII,EP3C40F780C8,NIOS II IDE, DDR II code
Nios_ii_8.0_back
- altera FPGA nios 实例,实现网络通信。-altera FPGA nios example, network communications.
Xilinx_ISE_PPT(whole)
- Xilinx_ISE_大学计划使用教程PPT(全) Xilinx_ISE_大学计划使用教程PPT_1包括:Xilinx公司产品概述,Xilinx公司软件平台介绍,Xilinx公司ISE10.1软件 设计流程介绍,PicoBlaze的8位微控制器概述,PicoBlaze的简单处理解决方案,PicoBlaze的一个实例,PicoBlaze指令集详解; Xilinx_ISE_大学计划使用教程PPT_2包括: PicoBlaze指令集详解,KCPSM3 汇编器,KCPSM3编程语法,KCPS
FpgaMskDemod
- 基于verilog编写的MSK解调FPGA代码,modsim仿真正确(MSK demodulation FPGA code based on Verilog, modsim simulation is correct)
Pre-Emphasis
- A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pree
example
- 基于Xilinx Spartan3E的去抖算法-Based on the Xilinx Spartan3E algorithm to Buffeting
fpgadsp.rar
- system gen & accel dsp 培训资料,system gen & accel dsp
jiaozhi_64
- VHDL语言实现按字节块交织,实现每64字节进行一次交织。-The VHDL language byte block interleaving, once every 64 bytes intertwined.
4-ADC模块
- ADC模块例程 适用于飞思卡尔电磁循迹小车等智能小车(ADC module routine is suitable for intelligent cars such as Freescale electromagnetic tracking car.)
laser_tracker
- laser_tracker in verilog
CPLD_Design_50
- CPLD实用设计50例,非常经典的CPLD设计,包含50个实际的典型应用,涉及直流电机PWM驱动,编码等内容,有了这50例,举一反三,就会了很多应用