资源列表
Verilog-HDL-Digital-Design
- Verilog HDL 数字设计与综合 夏宇闻-Verilog HDL Digital Design and Xia Wen
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
CCSK-FPGA
- 针对CCSK软扩频功能的实现，整理了很多资料，主要有CCSK软扩频原理以及FPGA实现，形成了一个完整的资料包，与大家分享-CCSK AND FPGA
aes
- 此程序完成aes的硬件语言实现部分，通过vhdl语言完成加解密过程。-This process is complete aes hardware language section, vhdl language to complete the encryption and decryption process.
SDRAM
- verilog编写的SDRAM实验，有串口调试助手和相关资料-Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!
VHDL_clock
- 运用VHDL写的时钟控制程序，状态机，时钟分频，频率变换。-VHDL clock
VHDL_Data
- 潘松的VHDL使用教程，已经制作书签，阅读方便，是学习VHDL新手的必备资料，FPGA/CPLD开发者可以参考的资料，-Pinson use of VHDL tutorial have produced bookmarks, reading easy to learn the essential information on VHDL novice, FPGA/CPLD developers can refer to the information,
FirFilterChol
- 在FPGA利用vhdl实现了32阶FIR滤波器。已经我利用了在几个对象。-In FPGA using VHDL to achieve a 32 order FIR filter. I ve used in many objects.
异步FIFO的简单设计
- 顶层连接读写模块，调用vivado IP核做缓存模块，实现读空、写满的设计
MC8051_test
- 基于SOPC的MCU51单片机内核的开发，需要使用51单片机内核的直接拿走。-MCU51 microcontroller core based SOPC development, requires the use of 51 microcontroller core directly away.
cputop
- cpu简单开发，利用verilog实现。 并进行下板实验(CPU is simply developed and implemented with Verilog. And carry out the experiment of the lower plate)
VHDL
- 一本很好的vhdl教程，适合所有初学者，是一本值得珍藏的好资料-A very good vhdl tutorial, suitable for all beginners, is a worthy collection of good information