资源列表
6FloorLift
- 设计一个6层电梯控制器。电梯控制器是按照乘客的要求自动上、下的装置。 1、每层电梯入口处设置上下请求开关，电梯内设有顾客到达层次的停站请求开关。 2、设有电梯所处位置指示装置以及电梯运行模式（上升或者下降）指示装置。 3、电梯每秒升降一层楼。 4、电梯到达有停站请求的楼层，经过1秒电梯门打开，开门4秒后，电梯门关闭（开门指示灯灭），电梯继续运行，直至执行完最后一个请求信号后停留在当前层。 5、电梯能记忆电梯内外所有请求信号，并按照电梯运行规则按顺序响应，每个请求信号保留至有电
dianti
- 在VHDL语言环境下实现6层楼的电梯控制系统-VHDL language environment in the realization of 6 floors of elevator control system
new_jilei15
- 脉冲累加器完成对15脉冲累加。用于雷达测距-inpuse add
basketballcounter
- a basketballscore counter two band 0--a basketballscore counter two band 0-999
dffasynchronous
- this ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element-this is ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element
MII_timing
- 用FPGA实现MII的数据传送时序控制,方法简单实用，设计及其精巧-implementation of MII data transmission’s timing control
slaveAHB
- amba总线的AHB部分，与从机相连接口的写法，载自其它网页。-amba AHB bus parts from the machine connected to the interface with the wording set out from other pages.
I2C
- I2C的Verilog HDL简单学习程序-The Verilog HDL simple I2C learning process
monitor
- driving monitor by xilinx xc2s200 fpga
PL_DPSK
- vhdl语言实现 dpsk调制以及解调 还有hdb3编码-vhdl language dpsk there hdb3 code modulation and demodulation
VerilogCode_time_of_day_clock
- Verilog Code for time-of-day clock and it is implemented on Altera DE2 board-Verilog Code for time-of-day clock and it is implemented on Altera DE2 board
hanming_HDL
- 汉明码编解码的两个例程，作为单元模块分别调入所开发系统-codec of two routines, as modules were transferred by the Development System