资源列表
arm
- 此程序是ARM+FPGA的总线通信程序，我只提供FPGA这一边的，其实我现在把这个程序移植到dsp+cpld上面去了，那个程序其实都出不多-This program is ARM+ FPGA bus communication procedures, I only FPGA side, in fact, I now put this program ported to dsp+ cpld go above, and that the program actually much
fir48
- 48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
decoder
- bch decoder 3072 3240 vhdl source code with ise software
IRIGDECODE
- IRIG-b 解码模块 采用VHDL编写，简单实用，已实测验证-IRIG-B DECODE VHDL
uart_fifo
- 一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。-This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.
FEJQR03IHWIQ3I9
- smart fan project for vhdl 5 part(2)
FVLI1QNIHWIQ3GD
- smart fan project for vhdl 5 part(xdc)
dfe_filter
- DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
my_emac
- modelsim仿真网口MAC收发数据包的实现代码-Modelsim simulation port MAC transceiver packet implementation code
usb_ctrl
- USB2.0 控制接口代码，可用于与上位机进行通信传输。-USB2.0 interface controller，can be used for communication between host(computer) and FPGA board.
usbf_crc5
- 适用于刚入门FPGA 的人使用，简单的FPGA程序例程-Applies to people who are just touching FPGAs
CNN
- 最简单的R3信道编解码，包含有测试程序，非常实用-The simplest R3 channel codec contains a test program that is very useful